View ADM1014JRU-REEL7_7550143.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. adm1014 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 rev. p r n 1/02 preliminary t echnical d ata dual pci hot-plug tm controller functional block diagram tm hot plug is a trademark of core international, inc. auxina vocset 100a ocset common to both channels 3.3vaux power-on reset low when auxina < 2.5v auxina 12vga 12vin a 5visena 5vsa 3visena 3vsa 3v5vga +5v in +3.3v in rsense3a rsense5a +5v outa +3.3v outa 12voa -12vga -12vina 5v regulator low when 12vina < 10v 35 34 37 36 33 -12voa 12vin a 12v in power-on reset gnd auxga auxina auxoa fltna fauxa 5 pwrona pauxona 12vin a circuit operates from 3.3vaux power supply circuit operates from 3.3vaux and +12v power supply p-channel mosfet d s g fault latch q q reset set overcurrent and undervoltage comparators for +5v overcurrent and undervoltage comparators for +3.3v p-channel mosfet d s g overcurrent and undervoltage comparators for +12v n-channel mosfet d s g overcurrent comparator for -12v fault latch q q reset set combining logic common to both channels channel a channel b ( identical to channel a ) 3 4 32 fltnb pwronb pauxonb 27 15 17 16 7 8 31 29 9 10 2 1 38 12vgb 12vinb 12vob -12vgb -12vinb 5visenb 23 5vsb 24 21 3visenb 3vsb 22 -12vob 3v5vgb 25 auxgb auxinb auxob 28 11 14 13 26 12 18 19 20 external n-channel power mosfets external n-channel power mosfets 3.3v cmos input 3.3v cmos output 30 30 overcurrent and undervoltage comparators for +3.3vaux +5v in +3.3v in rsense3b rsense5b +5v outa +3.3v outa channel a 6 +3.3vaux +3.3vaux fauxb
?2? rev. pr n 1/02 adm1014?specific a tions parameter min typ max units test conditions/comments 5v/ 3.3v supply control 5v overcurrent threshold - 8 - a see typical application diagram 5v overcurrent threshold voltage 33 42 50 mv v ocset = 0.6v 5v overcurrent threshold voltage 70 80 90 mv v ocset = 1.2v 5v undervoltage trip threshold 4.42 4.65 4.7 v 5v undervoltage fault response time - 110 160 ns 5v turn-on time - 9.75 - ms c 3v5vg = 0.033f, c 5vout = 2000f, (pwron high to 5vout = 4.75v) r l = 1 3v overcurrent threshold - 10 - a see typical application diagram 3v overcurrent threshold voltage 41 52 62 mv ocset = 0.6v 3v overcurrent threshold voltage 89 98 108 mv ocset = 1.2v 3v undervoltage trip threshold 2.74 2.86 2.9 v 3v undervoltage fault response time - 110 160 ns 3v5vg undervoltage enable threshold - 9.6 - v voltage 3v turn-on time - 9.75 - ms c 3v5vg = 0.033f, c 3vout = 2000f, (pwron high to 3vout = 3.00v) r l = 0.43 3v5vg vout high 11.5 11.8 - v pwron = high, fltn = high gate output charge current 19 25.0 29 a pwron = high, v 3v5vg = 4v gate turn-on time - 280 - s c 3v5vg = 0.033f, 3v5vg rising 10% to 90% (pwron high to 3v5vg = 11v) gate turn-off time - 2 - s c 3v5vg = 0.033f, 3v5vg falling 90% to 10% +12v supply control on resistance of internal pmos - 0.3 0.35 pwron = high, i d = 0.5a, t a = t j = 25 o c on resistance of internal pmos - 0.35 0.5 pwron = high, i d = 0.5a, t a = t j = 70 o c overcurrent threshold 0.6 0.75 0.9 a v ocset = 0.6v overcurrent threshold 1.25 1.50 1.8 a v ocset = 1.2v 12v undervoltage trip threshold 10.25 10.6 10.8 v undervoltage fault response time - 110 - ns (specifications are for each channel, 3.3vaux=auxina=3.3v, v cc = 12vin = +12v, -12vin = -12v, nominal 3.3v and 5v supplies to external mosfets, t a = 0 o c to +70 o c, unless otherwise noted.) features controls two pci slots controls all four pci supplies, +3.3v, +5v, +12v, -12v, plus 3.3v auxiliary supply internal mosfet switches for +3.3v aux, +12v and ?12v outputs adjustable overcurrent protection for all outputs undervoltage protection on +3.3v, +5v, +12v and +3.3v aux supplies open-drain fault output with adjustable delay logic control of outputs adjustable soft-start applications compact pci pci hot-plug tm general description the adm1014 is a dual pci voltage bus controller that allows hot-plugging of adapter cards into and out of an active or pas- sive backplane. the device requires only four external power mosfets and a few discrete components for a complete power-control solution for two pci slots. the adm1014 operates from a +12v and +3.3v aux supply and controls five independent supplies (+3.3v, +3.3vaux, +5v, +12v and ?12v) on two separate channels (a and b). the power switches for the +3.3vaux, +12v and ?12v supplies are integrated onto the chip, and internal current limiting is provided. for the +3.3v and +5v supplies, the device drives external, n-channel, power mosfets, and provides overcurrent protection by sensing the voltage drop across external current-sense resistors. the current limits for all 10 supplies are set by a single resistor to gnd, connected to the ocset pin. undervoltage sensing is provided on the +3.3v, +5v, +12v and +3.3vaux supplies. overcurrent sensing is provided on all supplies. in the event of an overcurrent or undervoltage fault on any of the outputs of either channel, all outputs on that channel will be turned off. turn-on slew rate may be controlled using eight external capacitors, connected to the gate drives of all of the supplies. logic control of the four main outputs is provided by the pwrona and pwronb pins. when these pins are high, the outputs are turned on, when low, the outputs are turned off. the +3.3vaux supplies have their own control inputs, pauxa and pauxb.
?3? rev. p r n 1/02 adm1014?specific a tions (continued) (specifications are for each channel, 3.3vaux=auxina=3.3v, v cc = 12vin = +12v, -12vin = -12v, nominal 3.3v and 5v supplies to external mosfets, t a = 0 o c to +70 o c, unless otherwise noted.) parameter min typ max units test conditions/comments gate charge current 19 25.0 29 a pwron = high, v 12vg = 10v turn-on time - 16 - ms c 12vg = 0.033f, 12vg falling 90% - 10% (pwron high to 12vg = 1v) turn-off time - 4.5 - s c 12vg = 0.033f, 12vg rising 10% - 90% -12v supply control on resistance of internal nmos - 0.7 1 pwron = high, i d = 0.1a, t a =t j =25 o c on resistance of internal nmos - 1 1.3 pwron = high, i d = 0.1a, t a =t j =70 o c overcurrent threshold 0.13 0.18 0.25 a v ocset = 0.6v overcurrent threshold 0.23 0.38 0.52 a v ocset = 1.2v gate output charge current 19 25 29 a pwron = high, v m12vg = -10v turn-on time - 16 - ms c m12vg = 0.033f, c m12vo = 50f,r l = 120 (pwron high to m12vo = -10.8v) turn-off time - 3 - s c m12vg =0.033f,m12vg falling 90% -10% m12vin input bias current - 2.5 5 ma pwron = high +3.3vaux supply control on resistance of internal pmos - 0.25 tbd pauxon = high, i d = 0.375a, t a =t j =25 o c on resistance of internal pmos - 0.25 tbd pauxon = h igh, i d = 0.375a, t a =t j =70 o c overcurrent threshold - 0.5 tbd a v ocset = 0.6v overcurrent threshold - 1.0 tbd a v ocset = 1.2v 3.3vaux undervoltage trip threshold - 2.9 tbd v undervoltage fault response time - 110 - ns gate charge current 19 25.0 29 a pauxon = high, v auxg = 3v turn-on time (pauxon high to auxg = 1v) - 16 - ms c auxg = 0.033f turn-off time - 3 - s c auxg = 0.033f, auxg rising 10% - 90% 3.3vaux power on reset threshold - 2.5 - v auxin voltage rising control pin s 12vin supply current - 5.3 8 ma auxin supply current - 3 tbd ma ocset current 93 100 107 a overcurrent to fault response time - 500 960 ns pwrona/b, pauxa/b threshold voltage 1.0 1.6 2.1 v 12v power on enable threshold 9.4 10 10.2 v 12vina voltage rising 12v power on reset threshold 8.9 9.1 9.3 v 12vina voltage falling fault o/p pin s output low voltage - 0.5 0.7 v i = 2ma output high voltage auxin -0.5 auxin -0.1 - v i = 0 output latch threshold tbd 1.6 tbd v i high to low transition
output low voltage - 0.5 0.7 v i
= 2ma
output high voltage auxin -0.5 auxin -0.1 - v i
= 0
output latch threshold tbd 1.6 tbd v i
high to low transition notes specifications subject to change without notice.
?4? rev. p r n 1/02 adm1014?specific a tions pin configuration absolute maximum ratings* (t a = +25c unless otherwise noted) v cc , 12vin . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +14.0v 12vo, 12vg, 3v5vg . . . . . . . . . . -0.5v to v 12vin +0.5v -12vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . -14.0v to +0.5v -12vo, -12vg . . . . . . . . . . . . . . . . . . . v -12vin -0.5v to +0.5v 3visen, 5visen . . . -0.5v to the lesser of 12vin or +7.0v voltage, any other pin . . . . . . . . . . . . . . . . . . -0.5v to +7.0v 12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3a -12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8a continuous power dissipation (t a = +70 o c) . . . . . . 667mw tssop (derate 8.3mw/ o c above +70 o c) operating temperature range commercial (j version) . . . . . . . . . . . . . . . . 0c to +70c storage temperature range . . . . . . . . . . . ?65c to +150c lead temperature (soldering, 10 sec) . . . . . . . . . . . +300c *this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this speci- fication is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. thermal characteristics 38-pin tssop package: q ja = 100c/watt, q jc = 10c/watt ordering guide temperature package package model range description option adm1014jru 0c to +70c 38-pin tssop ru-38 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 m12voa m12vga pwrona fltna fauxa ocset auxga auxoa 12vga 12voa 12vob 12vgb auxob auxgb fauxb fltnb pwronb m12vgb m12vob m12vina 3visena 3vsa 5visena 5vsa 3v5vga gnd auxina pauxona 12vina 12vinb pauxonb auxinb 3v5vgb 5vsb 5visenb 3vsb 3visenb m12vinb 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 adm1014 top view (not to scale)
adm1014 ?5? rev. p r n 1/02 pin function description pin mnemonic function 1 m12voa switched -12v output for channel a. rated for 100ma. 2 m12vga gate of channel a internal nmos transistor. a capacitor connected from this pin to -12voa (pin 1) sets the start-up ramp for the +12v supply. during turn-on, this capacitor is charged from a 25a current source. 3 pwrona power on control for channel a. 3.3v cmos-compatible logic input controls all four main supplies. pwrona high = outputs on, pwrona low = outputs off. 4 fltna active-low, 5v compatible, open drain fault output for channel a. a pull-up resistor connects the pin to 3.3vaux. 4.7k is recommended for this function. an optional capacitor may be connected from this pin to gnd to provide improved immunity to power supply transients. 5 fauxa active-low, 3.3v compatible, open drain fault output for aux channel a. the same pull-up resistor as that on fltna connects the pin to 3.3vaux. 6 ocset overcurrent set for all 10 outputs. a resistor connected from this pin to ground sets the overcurrent trip point of all eight supplies. all eight overcurrent trip-points can be programmed by changing the value of this resistor. the default value of 6.04k , 1% is compatible with the maximum currents allowed by the pci specification. 7 auxga gate of channel a +3.3vaux internal pmos transistor. a capacitor connected from this pin to auxoa (pin 8) sets the start-up ramp for the +3.3vaux supply. during turn-on, this capacitor is charged from a 25a current source. 8 auxoa switched 3.3v auxiliary output for channel a. rated for 0.375a. 9 12vga gate of channel a internal pmos transistor. a capacitor connected from this pin to 12voa (pin 10) sets the start-up ramp for the +12v supply. during turn-on, this capacitor is charged from a 25a current source. the undervoltage circuitry is disabled when the voltage on 12vga rises above 1.2v. if the capacitor on pin 7 (auxga) or pin 33 (3v5vga) is more than 25% larger than the capacitor on pin 9 (12vga) a false undervoltage condition may be detected during startup. 10 12voa switched 12v output for channel a. rated for 0.5a. 11 12vob switched 12v output for channel b. rated for 0.5a. 12 12vgb gate of channel b internal pmos transistor. a capacitor connected from this pin to 12vob (pin 11) sets the start-up ramp for the +12v supply. during turn-on, this capacitor is charged from a 25a current source. the undervoltage circuitry is disabled when the voltage on 12vgb rises above 1.2v. if the capacitor on the pin 25 (3v5vgb) or pin 14 (auxgb) is more t han 25% larger than the capacitor on pin 12 (12vgb) a false undervoltage condition may be detected during startup. 13 auxob switched 3.3v auxiliary output for channel b. rated for 0.375a. 14 auxgb gate of channel b +3.3vaux internal pmos transistor. a capacitor connected from this pin to auxob (pin 13) sets the start-up ramp for the +3.3vaux supply. during turn-on, this capacitor is charged from a 25a current source. 15 fauxb active-low, 3.3v compatible, open drain fault output for aux channel b. the same pull-up resistor as that on fltna connects the pin to 3.3vaux. 16 fltnb active-low, 5v compatible, open drain fault output for channel b. a pull-up resistor connects the pin to 3.3vaux. 4.7k is recommended for this function. an optional capacitor may be connected from this pin to gnd to provide improved immunity to power supply transients. 17 pwronb power on control for channel b. 3.3v cmos-compatible logic input controls all four main supplies. pwronb high = outputs on, pwronb low = outputs off. 18 m12vgb gate of channel b internal nmos transistor. a capacitor connected from this pin to -12vob (pin 19) sets the start-up ramp for the +12v supply. during turn-on, this capacitor is charged from a 25a current source. 19 m12vob switched -12v output for channel b. rated for 100ma.
adm1014 ?6? rev. p r n 1/02 p in function description (continued) pin mnemonic function 20 m12vinb -12v supply input for channel b. also provides power to the -12v overcurrent circuitry. 21 3visenb 3.3v current sense for channel b. a current-sensing resistor is connected between this pin and 3vsb (pin 22). connect to the load side of the current sense resistor. 22 3vsb 3.3v source for channel b. the source of the 3.3v mosfet is connected to this pin and a current-sensing resistor is connected between this pin and pin 21. 23 5visenb 5v current sense for channel b. a current-sensing resistor is connected between this pin and 5vsb (pin 24). connect to the load side of the current sense resistor. 24 5vsb 5v source for channel b. the source of the 5v mosfet is connected to this pin and a current-sensing resistor is connected between this pin and pin 23. 25 3v5vgb 3.3v and 5v gate output for channel b, drives the gates of the external 3.3v and 5v mosfets. a capacitor connected from this pin to gnd sets the start-up ramp for the 3.3v and 5v supplies. during turn-on, this capacitor is charged from a 25a current source. the undervoltage circuitry is disabled when the voltage on 3v5vgb falls below 12vin-1.2v. 26 auxinb +3.3v auxiliary supply input for channel b. 27 pauxonb power on control for channel b +3.3v auxiliary output. 3.3v cmos-compatible logic input. pauxonb high = outputs on, pauxonb low = outputs off. 28 12vinb switched +12v supply input for channel b. 29 12vina switched +12v supply input for channel a and for ocset and power-on reset circuits. 30 pauxona power on control for channel a +3.3v auxiliary output. 3.3v cmos-compatible logic input. pauxona high = outputs on, pauxona low = outputs off. 31 auxina +3.3v auxiliary supply input for channel a. 32 gnd ground for all chip circuits. connect to common of power supplies. 33 3v5vga 3.3v and 5v gate output for channel a, drives the gates of the external 3.3v and 5v mosfets. a capacitor connected from this pin to gnd sets the start-up ramp for the 3.3v and 5v supplies. during turn-on, this capacitor is charged from a 25a current source. the undervoltage circuitry is disabled when the voltage on 3v5vga falls below 12vin-1.2v. 34 5vsa 5v source for channel a. the source of the 5v mosfet is connected to this pin and a current-sensing resistor is connected between this pin and pin 35. 35 5visena 5v current sense for channel a. a current-sensing resistor is connected between this pin and 5vsa (pin 34). connect to the load side of the current sense resistor. 36 3vsa 3.3v source for channel a. the source of the 3.3v mosfet is connected to this pin and a current-sensing resistor is connected between this pin and pin 37. 37 3visena 3.3v current sense for channel a. a current-sensing resistor is connected between this pin and 3vsa (pin 36). connect to the load side of the current sense resistor. 38 m12vina -12v supply input for channel a. also provides power to the -12v overcurrent circuitry.
adm1014 ?7? rev. p r n 1/02 figure 1. simplified schematic current tracking and i-v converter v ocset /0.8 12vg 12vin 12vo -12vg -12vin comp comp comp comp comp comp inhibit inhibit inhibit zener reference 4.6v 2.9v 10.8v v ocset /14.5 v ocset /11.5 v ocset /3.3 current tracking and i-v converter -12vin v cc low when v cc < 10v v cc vocset 100a 5visen 5vs 3visen 3vs -12vo 3v5vg ocset v cc 12v in power-on reset gnd common to both channels circuit of one channel shown , both channels are identical. reset and ocset circuitry within dashed line is commeon to both channels comp current tracking and i-v converter v ocset /1.2 v c c auxg auxin auxo v cc flt faux v cc pwron comp v c c pauxon v cc 3v5vg
adm1014 ? 8 ? rev. p r n 1/02 functional description voltage outputs the adm1014 consists of two independent, identical chan- nels, a and b, each of which controls four main power supply voltages and an auxiliary voltage. as the channels are identical, the following description applies to either channel, except where otherwise stated. an on-chip pmos transistor connected between 12vin and 12vo switches the +12v supply at currents up to 1.5a, whilst an on-chip nmos transistor connected between -12vin and -12vo switches the ?12v supply at currents up to 0.38a. the +3.3v and +5v supplies are switched by external, n-channel mosfets, whose gate drive is provided by the 3v5vg pins. using suitable mosfets, singly or in parallel, currents of several amps may be switched with very low voltage drops. the four main power supplies may be switched on and off under control of the pwron pin. the 3.3v auxiliary supply has an on-chip pmos transistor, which can switch currents at up to 1a. this supply is con- trolled independently of the other four supplies by the pauxon pin. all five supplies are protected against overcurrent and the four positive supplies are also protected against undervoltage. external current limit the external power mosfets are protected and overcurrent shutdown is provided on the +3.3v and +5v supplies by exter- nal current-sense resistors and on-chip comparators. current-sensing resistors are connected between the +5v out- put pin and the 5visen pin, and between the +3.3v output pin and the 3.3visen pin. the sense pins are connected to the inverting inputs of the current-limit comparator directly, while the voltage outputs are connected to the non-inverting inputs via a reference voltage proportional to the voltage on the ocset pin. this voltage is v ocset /14.5 in the case of the 5v output and v ocset /11.5 in the case of the 3.3v output. these values were chosen so that the 3.3v and 5v sense resistors could both be 5m in pci applications. when the voltage drop across the current-sensing resistor ex- ceeds the reference voltage, the output of the comparator will go high, the fault latch will be set and all four main outputs and the auxiliary output on the channel will be turned off. the other main channel and auxiliary channel will remain on. the reference voltages for the current-limit comparators are set by connecting a resistor between the ocset pin and gnd. an on-chip, 100a current source generates a voltage across this resistor. the current limit may also be adjusted by the choice of current-sensing resistor. i limit (3.3v) = v ocset /(11.5 r sense3 ) = (r set 10 -4 )/(11.5 r sense3 ) i limit (5v) = v ocset /(14.5 r sense5 ) = (r set 10 -4 )/(14.5 r sense5 ) where: i limit = current limit in amps r set is resistor from ocset to gnd in r sense is current-sense resistor in note: the ocset current source obtains its power supply from 12vina. internal current limit the +3.3vaux, +12v and ?12v supplies have the power mosfet switches on-chip. these devices are protected and overcurrent shutdown is provided by a completely self-contained current sensing system. the output current through the on-chip power mosfet is tracked at a lower level by a second, smaller mosfet. the current through this mosfet is then con- verted to a voltage, which is compared to a reference voltage determined by r set . in the case of the +12v and -12v outputs, if the current-sense voltage exceeds this reference voltage, the comparator output will go high, the fault latch will be set and all four main outputs and the auxiliary output will be turned off. similarly in the case of the auxiliary output, if the current- sense voltage exceeds the reference voltage, the comparator output will go high, the fault latch will be set, fauxn/fltn will go low, and the auxiliary output and the four main outputs will turn off. the typical internal limiting currents may be calculated as follows: i limit (+3.3vaux) = v ocset /1.2 = (10-4 r set )/1.2 i limit (+12v) = 1.25 v ocset = 1.25 10-4 r set i limit (-12v) = v ocset /3.3 = (10-4 r set )/3.3 where: i limit = current limit in amps r set is resistor from ocset to gnd in due to tolerances in the current tracking fets, the variations in the internal current limit are quite wide, typically 20% of the calculated value for the +12v supply and +35/-20% of the calculated value for the ?12v supply. choice of r set and r sense using the above equations, r set is chosen to set the required current limits for the +3.3vaux, +12v and -12v supplies. once r set has been chosen, r sense3 and r sense5 can be chosen to set the current limits for the 3.3v and 5v outputs. for pci applications r set should be 6.04k and the current sense resistors should both be 5m 1%. this will set the cur- rent limits to the maximum values for the pci specification. for other applications, the following limits should be noted. 1. the minimum value of r set is limited by the minimum voltage the current?limit comparators can reliably sense, which is determined by noise, comparator offset voltage and the overdrive required to switch the comparator. the refer- ence voltage set by r set should not be less than 33mv for the 5v output, which has the smallest reference voltage. the minimum recommended value for r set is 6k , which gives a reference voltage of 35mv for the 5v output and 45mv for the 3.3v output. 2. the maximum value of r set is limited by the junction tem- perature. this is determined by the power dissipated in the on- chip mosfets, (which is dependent upon the current passed
adm1014 ? 9 ? rev. p r n 1/02 by the devices and their on-resistance), the thermal resistance of the package (100 o c/w), and the ambient temperature. the maximum on-resistance of the +3.3vaux mosfet is 0.65 , that of the +12v mosfet is 0.35 and that of the ? 12v mosfet is 0.9 , so the power dissipation will be: p d = (0.65 (i +3.3vaux ) 2 + 0.35 (i +12v ) 2 + 0.9 (i -12v ) 2 ) where: p d is power dissipation in watts i is current in amps under normal operating conditions the maximum recom- mended value for r set is 15k . undervoltage sensing undervoltage sensing of the +3.3v, +5v, +12v and +3.3vaux supplies is carried out by four voltage comparators. the supply voltages being monitoring are applied to the inverting inputs of these comparators, whilst reference voltages of 2.9v, 4.6v, 10.8v and 2.9v (derived from an on-chip zener reference) are applied to their non-inverting inputs. should any of the output voltages fall below the corresponding reference voltage, the output of the comparator will go high, the fault latch will be set, turning off all the supplies (main and auxiliary) on that channel. fltn and fauxn outputs the fltn and fauxn outputs are active-low, 3.3v compatible, open- drain fault outputs. these outputs are shorted together and then connected to the 3.3vaux supply using a 4.7k pull-up resistors. should an overcurrent or undervoltage event occur on one of the supplies, main or auxiliary, then the fault latch will be set, flta and fauxa or fltb and fauxb will go low and all outputs on the faulting channel will be turned off. programmable fault latch delay the delay between an overcurrent or undervoltage fault occur- ring and the outputs shutting down may be set by connecting a capacitor between a fltn or fauxn output and gnd. this delays the start of the fltn/fauxn output 1 to 0 transition and slows down the fall time of the fltn/fauxn output, thus delaying shutdown of the outputs. if the fault latch thresh- old (~1.6v) is reached on fltn/fauxn then the fault latch will be set and the four supply outputs and the auxiliary output will be shut down. if the fault disappears before the latching threshold is reached, the fault latch will not be set and the fltn/fauxn output will return to a high state. this adjustable delay allows the adm1014 to ignore overcurrent and undervoltage transients that might otherwise cause an un- wanted shutdown. it should be noted that if a fault is asserted on fltn and fauxn at the same time, then the delay is halved, as shown in fig. 2 and table 1. figure 2. fltn and 3v5vg delay table 1. flt and 3v5vg delay vs. c flt c flt t a t 2a open 0.1s 0.05s 0.001f 0.44s 0.22s 0.01f 2.9s 1.5s 0.1f 28s 14s power control inputs the pwrona and pwronb inputs are 3.3v cmos-com- patible logic inputs, which may be used to switch all four main outputs on and off, and is also used to reset the fault latch and turn the outputs back on after an overcurrent or undervoltage shutdown. when pwron is high, the four main s upplies are turned on. with pwron held low, the supplies are turned off. after an overcurrent or undervoltage shutdown, pwron should be toggled low then high again to reset the fault latch and turn on the outputs. pauxona and pauxonb are also 3.3v cmos-compatible logic inputs which perform a similar function for the +3.3v auxiliary supplies. power-on sequence and soft start when the device is powered on with pwron held high, the outputs are inhibited by the power-on reset circuit and will not become active until v cc exceeds 10v. during this time the undervoltage comparators are inhibited and the fault latch is held in a reset condition. note: the power-on reset circuit monitors 12vina. after the power-on delay, all five outputs are turned on simulta- neously. the undervoltage comparators are enabled when the voltage on the gate of the internal pmos transistor, 12vg, has fallen below about 400mv. the rise time of the outputs may be controlled by connecting capacitors between the gate and output pins of the +3.3vaux, +12v and -12v outputs, and from the 3v5vg pin to gnd. during output turn-on, these capacitors are charged from a nominal 25a current source. limiting the output rise times also limits the charging currents drawn by any supply decoupling capacitors in the circuits being driven. with fast turn-on these currents might be excessive and cause overcurrent faults at power-on. care must be taken when choosing these capacitors. if the capacitor on auxg or 3v5vg is more than 25% larger than
adm1014 ? 10 ? rev. p r n 1/02 figure 3. typical application circuit the capacitor on 12vg, the +3.3vaux, 3.3v and 5v outputs may not have exceeded their undervoltage thresholds by the time the undervoltage comparators are enabled, and a false undervoltage condition may be detected. for this reason it is recommended to use the same value for all three gate capaci- tors. for pci applications the minimum rec ommended value is 0.033f. smaller values may cause overcurrent faults at power- up due to excessive charging currents drawn by decoupling capacitors. the maximum value of the gate capacitors is determined by the need to discharge them quickly when turning off the outputs under fault conditions. if the capacitors are too large the adm1014 may be unable to protect the power bus or the ex- ternal mosfets. with 0.033f capacitors, the turn-off time will be less than 6s. applications information application circuit figure 3 shows a typical circuit configuration for the adm1014 in a pci application, controlling supply voltages of +3.3v at up to 7.6a, +5v at up to 5a, +12v at up to 0.5a and ?12v at up to 0.1a. in this circuit, two external mosfets are connected in parallel for the 3.3v and 5v outputs to minimise on-resistance. ocset gnd r5 c11 c 12 m12vob m12gb pwrona m12vina 12vob 12vina 3visena 3vsa 3v5vga 3visenb 3vsb 3v5vgb 12vinb m12vinb 5vsb 5visenb m12voa m12ga 12vga 12voa 5vsa 5visena adm1014 c2 c3 c4 c5 r1 r2 r3 r4 q1 q2 q3 q4 to system controller slot 2 5v 3.3v c7 c8 slot 1 -12v 12v auxina auxoa auxga c1 +3.3vaux 3.3v 5v +3.3vaux bus -12v 12v auxinb auxob auxgb c6 +3.3vaux fltna c10 12vgb pwronb pauxona pauxonb fauxa fltnb fauxb 5v bus 3.3v bus +12v bus -12v bus from system controller r11 r12 c9
adm1014 ? 11 ? rev. p r n 1/02 3.3vaux 3.3v 5.0v -12v 375ma 3a 2a 50ma +12v gnd 250ma rl5 rl4 rl3 rl2 rl1 c1 c2 c3 c4 c5 figure 4. load board for typical application circuit main board components item qty ref des description 1 1 u1 adm1014 2 1 skt1 38 pin tssop socket 3 4 q1-4 irf7413 power mosfet 4 4 d1-4 green smd led 5 4 r1-4 5m metal strip resistor 6 2 r5-6 470 0805 chip resistor 7 2 r7-8 1k5 0805 chip resistor 8 2 r9-10 6k04 0805 chip resistor 9 8 c1-8 cap,0.033uf 10 4 c9-12 cap,0.47uf 11 3 c13-15 electrolytic capacitor space 12 1 s1 spdt slide switch 13 8 t1-8 testpoint 14 2 p1-2 20 pin edge conn skt 15 4 j1 j4-j6 4mm 10a pcb sockets-red 16 1 j2 4mm 10a pcb sockets-green 17 1 j3 4mm 10a pcb sockets-black 18 4 p4-7 smb 19 1 pcb eval-adm1014 main board 20 4 r11-12 4k7 0805 chip resistor 21 2 load board fully assembled load board load board components item qty ref des description 1 1 pcb eval-adm1014load board 2 3 cl1-cl3 100uf 16v electrolytic caps 3 2 cl4-cl5 2200uf 16v electrolytic caps 4 1 rl1 47 6w (w22 series) res 5 1 rl2 240 2.5w (w21 series) res 6 1 rl3 10 6w (w22 series) res 7 1 rl4 2.2 12w (w24 series) res 8 1 rl5 1 12w (w24 series) res
adm1014 ? 12 ? rev. p r n 1/02 layout considerations any circuits supplied by the adm1014 are outside the control loops of the main system power supplies, which means that any series resistance between the four supply inputs and the out- puts will cause a degradation of the supply load regulation. this includes connector contact resistance, pcb trace resistance, on- resistance of mosfets (both external and on-chip) and current sense resistors. care must therefore be taken to ensure that: a) pcb traces are as heavy as possible. b)external mosfets have low-on resistance. c) current sense resistors are as small as possible. the current sense resistors have very small values (5m in the preceding example) to minimise the voltage drop across them. because of this, pcb trace resistance can be a significant per- centage of the sense resistance. it is therefore essential to en- sure that the adm1014 senses the voltage drop directly across the sense resistors and not across any current-carrying trace resistance in series with them. connections from the adm1014 to the sense resistors must go directly to the ends of the resistors. figure 4 shows examples of good and bad practice outline dimensions dimensions shown in inches and (mm). 38-pin tssop (ru-38) incorrect 35 34 37 36 22 21 24 23 current sense resistors vsense adm1014 vsense correct additional voltage drop additional voltage drop current sense resistors vsense adm1014 vsense additional voltage drop additional voltage drop 35 34 37 36 22 21 24 23 34 21 figure 4. good and bad practice for sense resistor connection 38 20 19 1 0.386 (9.80) 0.378 (9.60) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0200 (0.50) bsc 0.0433 (1.10) max 0.0106 (0.27) 0.0067 (0.17) 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 88 08

▲Up To Search▲

Price & Availability of ADM1014JRU-REEL7

	To Download ADM1014JRU-REEL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .